blake2/simd/
simdop.rs

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1// Copyright 2015 blake2-rfc Developers
2//
3// Licensed under the Apache License, Version 2.0, <LICENSE-APACHE or
4// http://apache.org/licenses/LICENSE-2.0> or the MIT license <LICENSE-MIT or
5// http://opensource.org/licenses/MIT>, at your option. This file may not be
6// copied, modified, or distributed except according to those terms.
7
8#[cfg(feature = "simd")]
9use crate::simd::simdint;
10use crate::simd::simdty::{u32x4, u64x4};
11
12use core::ops::{Add, BitXor, Shl, Shr};
13
14macro_rules! impl_ops {
15    ($vec:ident) => {
16        impl Add for $vec {
17            type Output = Self;
18
19            #[cfg(feature = "simd")]
20            #[inline(always)]
21            fn add(self, rhs: Self) -> Self::Output {
22                unsafe { simdint::simd_add(self, rhs) }
23            }
24
25            #[cfg(not(feature = "simd"))]
26            #[inline(always)]
27            fn add(self, rhs: Self) -> Self::Output {
28                $vec::new(
29                    self.0.wrapping_add(rhs.0),
30                    self.1.wrapping_add(rhs.1),
31                    self.2.wrapping_add(rhs.2),
32                    self.3.wrapping_add(rhs.3),
33                )
34            }
35        }
36
37        impl BitXor for $vec {
38            type Output = Self;
39
40            #[cfg(feature = "simd")]
41            #[inline(always)]
42            fn bitxor(self, rhs: Self) -> Self::Output {
43                unsafe { simdint::simd_xor(self, rhs) }
44            }
45
46            #[cfg(not(feature = "simd"))]
47            #[inline(always)]
48            fn bitxor(self, rhs: Self) -> Self::Output {
49                $vec::new(
50                    self.0 ^ rhs.0,
51                    self.1 ^ rhs.1,
52                    self.2 ^ rhs.2,
53                    self.3 ^ rhs.3,
54                )
55            }
56        }
57
58        impl Shl<$vec> for $vec {
59            type Output = Self;
60
61            #[cfg(feature = "simd")]
62            #[inline(always)]
63            fn shl(self, rhs: Self) -> Self::Output {
64                unsafe { simdint::simd_shl(self, rhs) }
65            }
66
67            #[cfg(not(feature = "simd"))]
68            #[inline(always)]
69            fn shl(self, rhs: Self) -> Self::Output {
70                $vec::new(
71                    self.0 << rhs.0,
72                    self.1 << rhs.1,
73                    self.2 << rhs.2,
74                    self.3 << rhs.3,
75                )
76            }
77        }
78
79        impl Shr<$vec> for $vec {
80            type Output = Self;
81
82            #[cfg(feature = "simd")]
83            #[inline(always)]
84            fn shr(self, rhs: Self) -> Self::Output {
85                unsafe { simdint::simd_shr(self, rhs) }
86            }
87
88            #[cfg(not(feature = "simd"))]
89            #[inline(always)]
90            fn shr(self, rhs: Self) -> Self::Output {
91                $vec::new(
92                    self.0 >> rhs.0,
93                    self.1 >> rhs.1,
94                    self.2 >> rhs.2,
95                    self.3 >> rhs.3,
96                )
97            }
98        }
99    };
100}
101
102impl_ops!(u32x4);
103impl_ops!(u64x4);
blake2/simd/simdop.rs

blake2/simd/
simdop.rs
