openvm_rv32im_transpiler/
instructions.rs

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1// =================================================================================================
2// RV32IM support opcodes.
3// Enum types that do not start with Rv32 can be used for generic big integers, but the default
4// offset is reserved for RV32IM.
5//
6// Create a new wrapper struct U256BaseAluOpcode(pub BaseAluOpcode) with the LocalOpcode macro to
7// specify a different offset.
8// =================================================================================================
9
10use openvm_instructions::LocalOpcode;
11use openvm_instructions_derive::LocalOpcode;
12use serde::{Deserialize, Serialize};
13use strum::{EnumCount, EnumIter, FromRepr};
14
15#[derive(
16    Copy,
17    Clone,
18    Debug,
19    PartialEq,
20    Eq,
21    PartialOrd,
22    Ord,
23    EnumCount,
24    EnumIter,
25    FromRepr,
26    LocalOpcode,
27    Serialize,
28    Deserialize,
29)]
30#[opcode_offset = 0x200]
31#[repr(usize)]
32pub enum BaseAluOpcode {
33    ADD,
34    SUB,
35    XOR,
36    OR,
37    AND,
38}
39
40#[derive(
41    Copy,
42    Clone,
43    Debug,
44    PartialEq,
45    Eq,
46    PartialOrd,
47    Ord,
48    EnumCount,
49    EnumIter,
50    FromRepr,
51    LocalOpcode,
52    Serialize,
53    Deserialize,
54)]
55#[opcode_offset = 0x205]
56#[repr(usize)]
57pub enum ShiftOpcode {
58    SLL,
59    SRL,
60    SRA,
61}
62
63#[derive(
64    Copy,
65    Clone,
66    Debug,
67    PartialEq,
68    Eq,
69    PartialOrd,
70    Ord,
71    EnumCount,
72    EnumIter,
73    FromRepr,
74    LocalOpcode,
75    Serialize,
76    Deserialize,
77)]
78#[opcode_offset = 0x208]
79#[repr(usize)]
80pub enum LessThanOpcode {
81    SLT,
82    SLTU,
83}
84
85#[derive(
86    Copy,
87    Clone,
88    Debug,
89    PartialEq,
90    Eq,
91    PartialOrd,
92    Ord,
93    EnumCount,
94    EnumIter,
95    FromRepr,
96    LocalOpcode,
97    Serialize,
98    Deserialize,
99)]
100#[opcode_offset = 0x210]
101#[repr(usize)]
102pub enum Rv32LoadStoreOpcode {
103    LOADW,
104    /// LOADBU, LOADHU are unsigned extend opcodes, implemented in the same chip with LOADW
105    LOADBU,
106    LOADHU,
107    STOREW,
108    STOREH,
109    STOREB,
110    /// The following are signed extend opcodes
111    LOADB,
112    LOADH,
113}
114
115#[derive(
116    Copy,
117    Clone,
118    Debug,
119    PartialEq,
120    Eq,
121    PartialOrd,
122    Ord,
123    EnumCount,
124    EnumIter,
125    FromRepr,
126    LocalOpcode,
127    Serialize,
128    Deserialize,
129)]
130#[opcode_offset = 0x220]
131#[repr(usize)]
132#[allow(non_camel_case_types)]
133pub enum BranchEqualOpcode {
134    BEQ,
135    BNE,
136}
137
138#[derive(
139    Copy,
140    Clone,
141    Debug,
142    PartialEq,
143    Eq,
144    PartialOrd,
145    Ord,
146    EnumCount,
147    EnumIter,
148    FromRepr,
149    LocalOpcode,
150    Serialize,
151    Deserialize,
152)]
153#[opcode_offset = 0x225]
154#[repr(usize)]
155#[allow(non_camel_case_types)]
156pub enum BranchLessThanOpcode {
157    BLT,
158    BLTU,
159    BGE,
160    BGEU,
161}
162
163#[derive(
164    Copy, Clone, Debug, PartialEq, Eq, PartialOrd, Ord, EnumCount, EnumIter, FromRepr, LocalOpcode,
165)]
166#[opcode_offset = 0x230]
167#[repr(usize)]
168#[allow(non_camel_case_types)]
169pub enum Rv32JalLuiOpcode {
170    JAL,
171    LUI,
172}
173
174#[derive(
175    Copy, Clone, Debug, PartialEq, Eq, PartialOrd, Ord, EnumCount, EnumIter, FromRepr, LocalOpcode,
176)]
177#[opcode_offset = 0x235]
178#[repr(usize)]
179#[allow(non_camel_case_types)]
180pub enum Rv32JalrOpcode {
181    JALR,
182}
183
184#[derive(
185    Copy, Clone, Debug, PartialEq, Eq, PartialOrd, Ord, EnumCount, EnumIter, FromRepr, LocalOpcode,
186)]
187#[opcode_offset = 0x240]
188#[repr(usize)]
189#[allow(non_camel_case_types)]
190pub enum Rv32AuipcOpcode {
191    AUIPC,
192}
193
194#[derive(
195    Copy, Clone, Debug, PartialEq, Eq, PartialOrd, Ord, EnumCount, EnumIter, FromRepr, LocalOpcode,
196)]
197#[opcode_offset = 0x250]
198#[repr(usize)]
199#[allow(non_camel_case_types)]
200pub enum MulOpcode {
201    MUL,
202}
203
204#[derive(
205    Copy,
206    Clone,
207    Debug,
208    PartialEq,
209    Eq,
210    PartialOrd,
211    Ord,
212    EnumCount,
213    EnumIter,
214    FromRepr,
215    LocalOpcode,
216    Serialize,
217    Deserialize,
218)]
219#[opcode_offset = 0x251]
220#[repr(usize)]
221#[allow(non_camel_case_types)]
222pub enum MulHOpcode {
223    MULH,
224    MULHSU,
225    MULHU,
226}
227
228#[derive(
229    Copy,
230    Clone,
231    Debug,
232    PartialEq,
233    Eq,
234    PartialOrd,
235    Ord,
236    EnumCount,
237    EnumIter,
238    FromRepr,
239    LocalOpcode,
240    Serialize,
241    Deserialize,
242)]
243#[opcode_offset = 0x254]
244#[repr(usize)]
245#[allow(non_camel_case_types)]
246pub enum DivRemOpcode {
247    DIV,
248    DIVU,
249    REM,
250    REMU,
251}
252
253// =================================================================================================
254// Rv32HintStore Instruction
255// =================================================================================================
256
257#[derive(
258    Copy, Clone, Debug, PartialEq, Eq, PartialOrd, Ord, EnumCount, EnumIter, FromRepr, LocalOpcode,
259)]
260#[opcode_offset = 0x260]
261#[repr(usize)]
262#[allow(non_camel_case_types)]
263pub enum Rv32HintStoreOpcode {
264    HINT_STOREW,
265    HINT_BUFFER,
266}
267
268// =================================================================================================
269// Phantom opcodes
270// =================================================================================================
271
272#[derive(Copy, Clone, Debug, PartialEq, Eq, FromRepr)]
273#[repr(u16)]
274pub enum Rv32Phantom {
275    /// Prepare the next input vector for hinting, but prepend it with a 4-byte decomposition of its length instead of one field element.
276    HintInput = 0x20,
277    /// Peek string from memory and print it to stdout.
278    PrintStr,
279    /// Prepare given amount of random numbers for hinting.
280    HintRandom,
281}
openvm_rv32im_transpiler/instructions.rs

openvm_rv32im_transpiler/
instructions.rs
