Expand description
RISC-V instruction set simulator library
Containts the building blocks for a RISC-V ISS. The seperate rrs-cli uses rrs-lib to implement a CLI driven ISS.
Re-exports§
pub use process_instruction::process_instruction;
Modules§
- instruction_
executor - An InstructionProcessor that executes instructions.
- instruction_
formats - Structures and constants for instruction decoding
- instruction_
string_ outputter - An InstructionProcessor that outputs a string of the instruction disassembly
- memories
- Various Memory implementations useful for an ISS and utility functions
- process_
instruction
Structs§
- Hart
State - State of a single RISC-V hart (hardware thread)
Enums§
- MemAccess
Size - The different sizes used for memory accesses
Traits§
- Instruction
Processor - A trait for objects which do something with RISC-V instructions (e.g. execute them or print a disassembly string).
- Memory
- A trait for objects which implement memory operations