Modules§
Structs§
- Base
AluCore Air - Base
AluCore Chip - Base
AluCore Cols - Base
AluCore Record - Branch
Equal Core Air - Branch
Equal Core Chip - Branch
Equal Core Cols - Branch
Equal Core Record - Branch
Less Than Core Air - Branch
Less Than Core Chip - Branch
Less Than Core Cols - Branch
Less Than Core Record - DivRem
Core Air - DivRem
Core Chip - DivRem
Core Cols - DivRem
Core Record - Less
Than Core Air - Less
Than Core Chip - Less
Than Core Cols - Less
Than Core Record - Load
Sign Extend Core Air - Load
Sign Extend Core Chip - Load
Sign Extend Core Cols - LoadSignExtend Core Chip handles byte/halfword into word conversions through sign extend This chip uses read_data to construct write_data prev_data columns are not used in constraints defined in the CoreAir, but are used in constraints by the Adapter shifted_read_data is the read_data shifted by (shift_amount & 2), this reduces the number of opcode flags needed using this shifted data we can generate the write_data as if the shift_amount was 0 for loadh and 0 or 1 for loadb
- Load
Sign Extend Core Record - Load
Store Core Air - Load
Store Core Chip - Load
Store Core Cols - LoadStore Core Chip handles byte/halfword into word conversions and unsigned extends This chip uses read_data and prev_data to constrain the write_data It also handles the shifting in case of not 4 byte aligned instructions This chips treats each (opcode, shift) pair as a separate instruction
- Load
Store Core Record - MulH
Core Air - MulH
Core Chip - MulH
Core Cols - MulH
Core Record - Multiplication
Core Air - Multiplication
Core Chip - Multiplication
Core Cols - Multiplication
Core Record - Rv32
Auipc Core Air - Rv32
Auipc Core Chip - Rv32
Auipc Core Cols - Rv32
Auipc Core Record - Rv32
Hint Store Air - Rv32
Hint Store Chip - Rv32
Hint Store Cols - Rv32
Hint Store Record - Rv32I
- RISC-V 32-bit Base (RV32I) Extension
- Rv32I
Config - Config for a VM with base extension and IO extension
- Rv32
ImConfig - Config for a VM with base extension, IO extension, and multiplication extension
- Rv32Io
- RISC-V Extension for handling IO (not to be confused with I base extension)
- Rv32
JalLui Core Air - Rv32
JalLui Core Chip - Rv32
JalLui Core Cols - Rv32
JalLui Core Record - Rv32
Jalr Core Air - Rv32
Jalr Core Chip - Rv32
Jalr Core Cols - Rv32
Jalr Core Record - Rv32M
- RISC-V 32-bit Multiplication Extension (RV32M) Extension
- Shift
Core Air - Shift
Core Chip - Shift
Core Cols - Shift
Core Record
Enums§
- Rv32I
Config Executor - Rv32I
Config Periphery - Rv32I
Executor - RISC-V 32-bit Base (RV32I) Instruction Executors
- Rv32I
Periphery - Rv32
ImConfig Executor - Rv32
ImConfig Periphery - Rv32
IoExecutor - RISC-V 32-bit Io Instruction Executors
- Rv32
IoPeriphery - Rv32M
Executor - RISC-V 32-bit Multiplication Extension (RV32M) Instruction Executors
- Rv32M
Periphery