LoadSignExtend Core Chip handles byte/halfword into word conversions through sign extend
This chip uses read_data to construct write_data
prev_data columns are not used in constraints defined in the CoreAir, but are used in constraints by the Adapter
shifted_read_data is the read_data shifted by (shift_amount & 2), this reduces the number of opcode flags needed
using this shifted data we can generate the write_data as if the shift_amount was 0 for loadh and 0 or 1 for loadb
LoadStore Core Chip handles byte/halfword into word conversions and unsigned extends
This chip uses read_data and prev_data to constrain the write_data
It also handles the shifting in case of not 4 byte aligned instructions
This chips treats each (opcode, shift) pair as a seperate instruction
HintStore Core Chip handles the range checking of the data to be written to memory
RISC-V 32-bit Base (RV32I) Extension
Config for a VM with base extension and IO extension
Config for a VM with base extension, IO extension, and multiplication extension
RISC-V Extension for handling IO (not to be confused with I base extension)
RISC-V 32-bit Multiplication Extension (RV32M) Extension