LoadStore Adapter handles all memory and register operations, so it must be aware
of the instruction type, specifically whether it is a load or store
LoadStore Adapter handles 4 byte aligned lw, sw instructions,
2 byte aligned lh, lhu, sh instructions and
1 byte aligned lb, lbu, sb instructions
This adapter always batch reads/writes 4 bytes,
thus it needs to shift left the memory pointer by some amount in case of not 4 byte aligned intermediate pointers
Reads instructions of the form OP a, b, c, d, e where [a:4]_d = [b:4]_d op [c:4]_e.
Operand d can only be 1, and e can be either 1 (for register reads) or 0 (when c
is an immediate).
Reads instructions of the form OP a, b, c, d, e where if([a:4]_d op [b:4]_e) pc += c.
Operands d and e can only be 1.
This adapter doesn’t read anything, and maybe writes to [a:4]_d, where d == 1
This chip reads rs1 and gets a intermediate memory pointer address with rs1 + imm.
It writes to the memory at the intermediate pointer.
This chip reads rs1 and gets a intermediate memory pointer address with rs1 + imm.
In case of Loads, reads from the shifted intermediate pointer and writes to rd.
In case of Stores, reads from rs2 and writes to the shifted intermediate pointer.
The LoadStoreAdapter seperates Runtime and Air AdapterInterfaces.
This is necessary because prev_data should be owned by the core chip and sent to the adapter,
and it must have an AB::Var type in AIR as to satisfy the memory_bridge interface.
This is achived by having different types for reads and writes in Air AdapterInterface.
This method ensures that there are no modifications to the global interfaces.
Reads instructions of the form OP a, b, c, d where [a:4]_d = [b:4]_d op [c:4]_d.
Operand d can only be 1, and there is no immediate support.
This adapter doesn’t read anything, and writes to [a:4]_d, where d == 1