Trait VmCoreChip

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pub trait VmCoreChip<F, I: VmAdapterInterface<F>> {
    type Record: Send + Serialize + DeserializeOwned;
    type Air: BaseAirWithPublicValues<F> + Clone;

    // Required methods
    fn execute_instruction(
        &self,
        instruction: &Instruction<F>,
        from_pc: u32,
        reads: I::Reads,
    ) -> Result<(AdapterRuntimeContext<F, I>, Self::Record)>;
    fn get_opcode_name(&self, opcode: usize) -> String;
    fn generate_trace_row(&self, row_slice: &mut [F], record: Self::Record);
    fn air(&self) -> &Self::Air;

    // Provided methods
    fn generate_public_values(&self) -> Vec<F> { ... }
    fn finalize(&self, _trace: &mut RowMajorMatrix<F>, _num_records: usize) { ... }
}
Expand description

Trait to be implemented on primitive chip to integrate with the machine.

Required Associated Types§

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type Record: Send + Serialize + DeserializeOwned

Minimum data that must be recorded to be able to generate trace for one row of PrimitiveAir.

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type Air: BaseAirWithPublicValues<F> + Clone

The primitive AIR with main constraints that do not depend on memory and other architecture-specifics.

Required Methods§

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fn execute_instruction( &self, instruction: &Instruction<F>, from_pc: u32, reads: I::Reads, ) -> Result<(AdapterRuntimeContext<F, I>, Self::Record)>

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fn get_opcode_name(&self, opcode: usize) -> String

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fn generate_trace_row(&self, row_slice: &mut [F], record: Self::Record)

Populates row_slice with values corresponding to record. The provided row_slice will have length equal to self.air().width(). This function will be called for each row in the trace which is being used, and all other rows in the trace will be filled with zeroes.

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fn air(&self) -> &Self::Air

Provided Methods§

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fn generate_public_values(&self) -> Vec<F>

Returns a list of public values to publish.

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fn finalize(&self, _trace: &mut RowMajorMatrix<F>, _num_records: usize)

Finalize the trace, especially the padded rows if the all-zero rows don’t satisfy the constraints. This is done after records are consumed and the trace matrix is generated. Most implementations should just leave the default implementation if padding with rows of all 0s satisfies the constraints.

Implementors§

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impl<F: PrimeField32> VmCoreChip<F, BasicAdapterInterface<F, MinimalInstruction<F>, 2, 0, 1, 1>> for PublicValuesCoreChip<F>

impl<F: PrimeField32, I: VmAdapterInterface<F>, const READ_LIMBS: usize, const WRITE_LIMBS: usize, const LIMB_BITS: usize> VmCoreChip<F, I> for ModularIsEqualCoreChip<READ_LIMBS, WRITE_LIMBS, LIMB_BITS>

impl<F: PrimeField32, I: VmAdapterInterface<F>> VmCoreChip<F, I> for CastFCoreChip
where I::Reads: Into<[[F; 1]; 1]>, I::Writes: From<[[F; 4]; 1]>,

impl<F: PrimeField32, I: VmAdapterInterface<F>, const NUM_CELLS: usize> VmCoreChip<F, I> for NativeLoadStoreCoreChip<F, NUM_CELLS>

impl<F, I, const NUM_LIMBS: usize, const LIMB_BITS: usize> VmCoreChip<F, I> for BaseAluCoreChip<NUM_LIMBS, LIMB_BITS>

impl<F: PrimeField32, I: VmAdapterInterface<F>> VmCoreChip<F, I> for Rv32JalrCoreChip
where I::Reads: Into<[[F; 4]; 1]>, I::Writes: From<[[F; 4]; 1]>,

impl<F: PrimeField32, I: VmAdapterInterface<F>, const NUM_CELLS: usize> VmCoreChip<F, I> for LoadStoreCoreChip<NUM_CELLS>
where I::Reads: Into<([[F; NUM_CELLS]; 2], F)>, I::Writes: From<[[F; NUM_CELLS]; 1]>,

impl<F: PrimeField32, I: VmAdapterInterface<F>, const NUM_CELLS: usize, const LIMB_BITS: usize> VmCoreChip<F, I> for LoadSignExtendCoreChip<NUM_CELLS, LIMB_BITS>
where I::Reads: Into<([[F; NUM_CELLS]; 2], F)>, I::Writes: From<[[F; NUM_CELLS]; 1]>,

impl<F: PrimeField32, I: VmAdapterInterface<F>, const NUM_LIMBS: usize> VmCoreChip<F, I> for BranchEqualCoreChip<NUM_LIMBS>
where I::Reads: Into<[[F; NUM_LIMBS]; 2]>, I::Writes: Default,

impl<F: PrimeField32, I: VmAdapterInterface<F>, const NUM_LIMBS: usize, const LIMB_BITS: usize> VmCoreChip<F, I> for BranchLessThanCoreChip<NUM_LIMBS, LIMB_BITS>
where I::Reads: Into<[[F; NUM_LIMBS]; 2]>, I::Writes: Default,

impl<F: PrimeField32, I: VmAdapterInterface<F>, const NUM_LIMBS: usize, const LIMB_BITS: usize> VmCoreChip<F, I> for DivRemCoreChip<NUM_LIMBS, LIMB_BITS>

impl<F: PrimeField32, I: VmAdapterInterface<F>, const NUM_LIMBS: usize, const LIMB_BITS: usize> VmCoreChip<F, I> for LessThanCoreChip<NUM_LIMBS, LIMB_BITS>

impl<F: PrimeField32, I: VmAdapterInterface<F>, const NUM_LIMBS: usize, const LIMB_BITS: usize> VmCoreChip<F, I> for MulHCoreChip<NUM_LIMBS, LIMB_BITS>

impl<F: PrimeField32, I: VmAdapterInterface<F>, const NUM_LIMBS: usize, const LIMB_BITS: usize> VmCoreChip<F, I> for MultiplicationCoreChip<NUM_LIMBS, LIMB_BITS>

impl<F: PrimeField32, I: VmAdapterInterface<F>, const NUM_LIMBS: usize, const LIMB_BITS: usize> VmCoreChip<F, I> for ShiftCoreChip<NUM_LIMBS, LIMB_BITS>