Type Alias Rv32Shift256Chip

pub type Rv32Shift256Chip<F> = VmChipWrapper<F, Rv32HeapAdapterChip<F, 2, INT256_NUM_LIMBS, INT256_NUM_LIMBS>, ShiftCoreChip<INT256_NUM_LIMBS, RV32_CELL_BITS>>;

Aliased Type

struct Rv32Shift256Chip<F> {
    pub adapter: Rv32HeapAdapterChip<F, 2, 32, 32>,
    pub core: ShiftCoreChip<32, 8>,
    pub records: Vec<(<Rv32HeapAdapterChip<F, 2, INT256_NUM_LIMBS, INT256_NUM_LIMBS> as VmAdapterChip<F>>::ReadRecord, <Rv32HeapAdapterChip<F, 2, INT256_NUM_LIMBS, INT256_NUM_LIMBS> as VmAdapterChip<F>>::WriteRecord, <ShiftCoreChip<INT256_NUM_LIMBS, RV32_CELL_BITS> as VmCoreChip<F, <Rv32HeapAdapterChip<F, 2, INT256_NUM_LIMBS, INT256_NUM_LIMBS> as VmAdapterChip<F>>::Interface>>::Record)>,
    /* private fields */
}

Fields

adapter: Rv32HeapAdapterChip<F, 2, 32, 32>

core: ShiftCoreChip<32, 8>

records: Vec<(<Rv32HeapAdapterChip<F, 2, INT256_NUM_LIMBS, INT256_NUM_LIMBS> as VmAdapterChip<F>>::ReadRecord, <Rv32HeapAdapterChip<F, 2, INT256_NUM_LIMBS, INT256_NUM_LIMBS> as VmAdapterChip<F>>::WriteRecord, <ShiftCoreChip<INT256_NUM_LIMBS, RV32_CELL_BITS> as VmCoreChip<F, <Rv32HeapAdapterChip<F, 2, INT256_NUM_LIMBS, INT256_NUM_LIMBS> as VmAdapterChip<F>>::Interface>>::Record)>

Implementations

impl<F, A, C> VmChipWrapper<F, A, C>

where A: VmAdapterChip<F>, C: VmCoreChip<F, <A as VmAdapterChip<F>>::Interface>,

pub fn new( adapter: A, core: C, offline_memory: Arc<Mutex<OfflineMemory<F>>>, ) -> VmChipWrapper<F, A, C>

Trait Implementations

impl<SC, A, C> Chip<SC> for VmChipWrapper<<<<SC as StarkGenericConfig>::Pcs as Pcs<<SC as StarkGenericConfig>::Challenge, <SC as StarkGenericConfig>::Challenger>>::Domain as PolynomialSpace>::Val, A, C>

where SC: StarkGenericConfig, <<<SC as StarkGenericConfig>::Pcs as Pcs<<SC as StarkGenericConfig>::Challenge, <SC as StarkGenericConfig>::Challenger>>::Domain as PolynomialSpace>::Val: PrimeField32, A: VmAdapterChip<<<<SC as StarkGenericConfig>::Pcs as Pcs<<SC as StarkGenericConfig>::Challenge, <SC as StarkGenericConfig>::Challenger>>::Domain as PolynomialSpace>::Val> + Send + Sync, C: VmCoreChip<<<<SC as StarkGenericConfig>::Pcs as Pcs<<SC as StarkGenericConfig>::Challenge, <SC as StarkGenericConfig>::Challenger>>::Domain as PolynomialSpace>::Val, <A as VmAdapterChip<<<<SC as StarkGenericConfig>::Pcs as Pcs<<SC as StarkGenericConfig>::Challenge, <SC as StarkGenericConfig>::Challenger>>::Domain as PolynomialSpace>::Val>>::Interface> + Send + Sync, <A as VmAdapterChip<<<<SC as StarkGenericConfig>::Pcs as Pcs<<SC as StarkGenericConfig>::Challenge, <SC as StarkGenericConfig>::Challenger>>::Domain as PolynomialSpace>::Val>>::Air: Send + Sync + 'static + VmAdapterAir<SymbolicRapBuilder<<<<SC as StarkGenericConfig>::Pcs as Pcs<<SC as StarkGenericConfig>::Challenge, <SC as StarkGenericConfig>::Challenger>>::Domain as PolynomialSpace>::Val>> + for<'a> VmAdapterAir<DebugConstraintBuilder<'a, SC>>, <C as VmCoreChip<<<<SC as StarkGenericConfig>::Pcs as Pcs<<SC as StarkGenericConfig>::Challenge, <SC as StarkGenericConfig>::Challenger>>::Domain as PolynomialSpace>::Val, <A as VmAdapterChip<<<<SC as StarkGenericConfig>::Pcs as Pcs<<SC as StarkGenericConfig>::Challenge, <SC as StarkGenericConfig>::Challenger>>::Domain as PolynomialSpace>::Val>>::Interface>>::Air: Send + Sync + 'static + VmCoreAir<SymbolicRapBuilder<<<<SC as StarkGenericConfig>::Pcs as Pcs<<SC as StarkGenericConfig>::Challenge, <SC as StarkGenericConfig>::Challenger>>::Domain as PolynomialSpace>::Val>, <<A as VmAdapterChip<<<<SC as StarkGenericConfig>::Pcs as Pcs<<SC as StarkGenericConfig>::Challenge, <SC as StarkGenericConfig>::Challenger>>::Domain as PolynomialSpace>::Val>>::Air as VmAdapterAir<SymbolicRapBuilder<<<<SC as StarkGenericConfig>::Pcs as Pcs<<SC as StarkGenericConfig>::Challenge, <SC as StarkGenericConfig>::Challenger>>::Domain as PolynomialSpace>::Val>>>::Interface> + for<'a> VmCoreAir<DebugConstraintBuilder<'a, SC>, <<A as VmAdapterChip<<<<SC as StarkGenericConfig>::Pcs as Pcs<<SC as StarkGenericConfig>::Challenge, <SC as StarkGenericConfig>::Challenger>>::Domain as PolynomialSpace>::Val>>::Air as VmAdapterAir<DebugConstraintBuilder<'a, SC>>>::Interface>,

fn air(&self) -> Arc<dyn AnyRap<SC>>

fn generate_air_proof_input(self) -> AirProofInput<SC>

Generate all necessary input for proving a single AIR.

fn generate_air_proof_input_with_id( self, air_id: usize, ) -> (usize, AirProofInput<SC>)

impl<F, A, M> ChipUsageGetter for VmChipWrapper<F, A, M>

where A: VmAdapterChip<F> + Sync, M: VmCoreChip<F, <A as VmAdapterChip<F>>::Interface> + Sync,

fn air_name(&self) -> String

fn current_trace_height(&self) -> usize

Height of used rows in the main trace.

fn trace_width(&self) -> usize

Width of the main trace

fn constant_trace_height(&self) -> Option<usize>

If the chip has a state-independent trace height that is determined upon construction, return this height. This is used to distinguish “static” versus “dynamic” usage metrics.

fn current_trace_cells(&self) -> usize

For metrics collection

impl<F, A, M> InstructionExecutor<F> for VmChipWrapper<F, A, M>

where F: PrimeField32, A: VmAdapterChip<F> + Send + Sync, M: VmCoreChip<F, <A as VmAdapterChip<F>>::Interface> + Send + Sync,

fn execute( &mut self, memory: &mut MemoryController<F>, instruction: &Instruction<F>, from_state: ExecutionState<u32>, ) -> Result<ExecutionState<u32>, ExecutionError>

Runtime execution of the instruction, if the instruction is owned by the current instance. May internally store records of this call for later trace generation.

fn get_opcode_name(&self, opcode: usize) -> String

For display purposes. From absolute opcode as usize, return the string name of the opcode if it is a supported opcode by the present executor.