Trait TranspilerExtension 

pub trait TranspilerExtension<F> {
    // Required method
    fn process_custom(
        &self,
        instruction_stream: &[u32],
    ) -> Option<TranspilerOutput<F>>;

    // Provided method
    fn modify_initial_memory(
        &self,
        _init_memory: &mut SparseMemoryImage,
    ) -> Result<()> { ... }
}

Trait to add custom RISC-V instruction transpilation to OpenVM instruction format. RISC-V instructions always come in 32-bit chunks. An important feature is that multiple 32-bit RISC-V instructions can be transpiled into a single OpenVM instruction. See process_custom for details.

Required Methods

fn process_custom( &self, instruction_stream: &[u32], ) -> Option<TranspilerOutput<F>>

The instruction_stream provides a view of the remaining RISC-V instructions to be processed, presented as 32-bit chunks. The process_custom should determine if it knows how to transpile the next contiguous section of RISC-V instructions into an [Instruction]. It returns None if it cannot transpile. Otherwise it returns TranspilerOutput { instructions, used_u32s } to indicate that instruction_stream[..used_u32s] should be transpiled into instructions.

Provided Methods

fn modify_initial_memory( &self, _init_memory: &mut SparseMemoryImage, ) -> Result<()>

Each transpiler extension is given the opportunity to modify the initial memory state. By default, nothing is done.

Implementors