LoadStore Adapter handles all memory and register operations, so it must be aware
of the instruction type, specifically whether it is a load or store
LoadStore Adapter handles 4 byte aligned lw, sw instructions,
2 byte aligned lh, lhu, sh instructions and
1 byte aligned lb, lbu, sb instructions
This adapter always batch reads/writes 4 bytes,
thus it needs to shift left the memory pointer by some amount in case of not 4 byte aligned
intermediate pointers
Reads instructions of the form OP a, b, c, d, e where [a:4]_d = [b:4]_d op [c:4]_e.
Operand d can only be 1, and e can be either 1 (for register reads) or 0 (when c
is an immediate).
This chip reads rs1 and gets a intermediate memory pointer address with rs1 + imm.
In case of Loads, reads from the shifted intermediate pointer and writes to rd.
In case of Stores, reads from rs2 and writes to the shifted intermediate pointer.
Atomic read operation which increments the timestamp by 1.
Returns (t_prev, [ptr:4]_{address_space}) where t_prev is the timestamp of the last memory
access.
Reads register value at reg_ptr from memory and records the memory access in mutable buffer.
Trace generation relevant to this memory access can be done fully from the recorded buffer.
Writes reg_ptr, reg_val into memory and records the memory access in mutable buffer.
Trace generation relevant to this memory access can be done fully from the recorded buffer.