openvm_sha2_circuit/sha2_chips/main_chip/
columns.rs

1use openvm_circuit::{
2    arch::ExecutionState,
3    system::memory::offline_checker::{MemoryReadAuxCols, MemoryWriteAuxCols},
4};
5use openvm_circuit_primitives::ColsRef;
6use openvm_instructions::riscv::RV32_REGISTER_NUM_LIMBS;
7
8use crate::{Sha2MainChipConfig, SHA2_REGISTER_READS, SHA2_WRITE_SIZE};
9
10#[repr(C)]
11#[derive(Clone, Copy, Debug, ColsRef)]
12#[config(Sha2MainChipConfig)]
13pub struct Sha2Cols<T, const BLOCK_BYTES: usize, const STATE_BYTES: usize> {
14    pub block: Sha2BlockCols<T, BLOCK_BYTES, STATE_BYTES>,
15    pub instruction: Sha2InstructionCols<T>,
16    pub mem: Sha2MemoryCols<T, BLOCK_BYTES, STATE_BYTES, SHA2_WRITE_SIZE>,
17}
18
19#[repr(C)]
20#[derive(Clone, Copy, Debug, ColsRef)]
21#[config(Sha2MainChipConfig)]
22pub struct Sha2BlockCols<T, const BLOCK_BYTES: usize, const STATE_BYTES: usize> {
23    /// Identifier of this row in the interactions between the two chips
24    pub request_id: T,
25    /// Input bytes for this block
26    pub message_bytes: [T; BLOCK_BYTES],
27    /// Previous state of the SHA-2 hasher object, as little-endian words
28    pub prev_state: [T; STATE_BYTES],
29    /// New state of the SHA-2 hasher object after processing this block, as little-endian words
30    pub new_state: [T; STATE_BYTES],
31}
32
33#[repr(C)]
34#[derive(Clone, Copy, Debug, ColsRef)]
35#[config(Sha2MainChipConfig)]
36pub struct Sha2InstructionCols<T> {
37    /// True for all rows that are part of opcode execution.
38    /// False on dummy rows only used to pad the height.
39    pub is_enabled: T,
40    #[aligned_borrow]
41    pub from_state: ExecutionState<T>,
42    /// Pointer to address space 1 `dst` register
43    pub dst_reg_ptr: T,
44    /// Pointer to address space 1 `state` register
45    pub state_reg_ptr: T,
46    /// Pointer to address space 1 `input` register
47    pub input_reg_ptr: T,
48    // Register values
49    /// dst_ptr_limbs <- \[dst_reg_ptr:4\]_1
50    pub dst_ptr_limbs: [T; RV32_REGISTER_NUM_LIMBS],
51    /// state_ptr_limbs <- \[state_reg_ptr:4\]_1
52    pub state_ptr_limbs: [T; RV32_REGISTER_NUM_LIMBS],
53    /// input_ptr_limbs <- \[input_reg_ptr:4\]_1
54    pub input_ptr_limbs: [T; RV32_REGISTER_NUM_LIMBS],
55}
56
57#[repr(C)]
58#[derive(Clone, Copy, Debug, ColsRef)]
59#[config(Sha2MainChipConfig)]
60pub struct Sha2MemoryCols<
61    T,
62    const BLOCK_READS: usize,
63    const STATE_READS: usize,
64    const STATE_WRITES: usize,
65> {
66    #[aligned_borrow]
67    pub register_aux: [MemoryReadAuxCols<T>; SHA2_REGISTER_READS],
68    #[aligned_borrow]
69    pub input_reads: [MemoryReadAuxCols<T>; BLOCK_READS],
70    #[aligned_borrow]
71    pub state_reads: [MemoryReadAuxCols<T>; STATE_READS],
72    #[aligned_borrow]
73    pub write_aux: [MemoryWriteAuxCols<T, SHA2_WRITE_SIZE>; STATE_WRITES],
74}
openvm_sha2_circuit/sha2_chips/main_chip/columns.rs

openvm_sha2_circuit/sha2_chips/main_chip/
columns.rs
